1·Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
2·The second is where you have to integrate the loop closely with the sequential logic.
第二点是，人们必须将一些控制环与顺序逻辑控制更紧密地集成。
3·For sequential logic, the key is clock. Everything has to be synchronized with clock.
之前看的那些顺序逻辑的例子好像确实全都没有时钟信号。
4·This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.
本实验指导书分为两大部分：组合逻辑，时序逻辑。
5·The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.
这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。
6·In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
7·The race and hazard in the sequential logic circuit is quite essential and must be considered when designing logic circuit.
时序逻辑电路中的竞争冒险是电路设计中必须考虑到的重要方面。
8·It is demonstrated that the SRL can be used for both combinatorial and sequential logic functions, and as all-optical regeneration devices.
SRL不但可用来实现组合的和顺序的逻辑功能，还可用于全光再生器件。
9·The principle of using sequential logic circuit and 8031 monolithic computer for realizing continuous pulse duration measure are introduced.
主要介绍了用时序逻辑电路实现连续脉冲宽度测量的工作原理，并讨论了采用8031单片机的实现方案。
10·This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.
本文给出一个时序逻辑电路的多故障测试模拟程序。